1. Field of the Invention
The present invention generally relates to semiconductor memories, either stand-alone or embedded in more complex integrated circuit electronic systems. In particular, the invention relates to an improved sensing circuit for a semiconductor memory.
2. Discussion of the Related Art
Semiconductor memories are commonly used in several applications for storing information, both temporarily (in so-called volatile memories), and permanently (in so-called non-volatile memories). Non-volatile memories are capable of retaining the stored information even in absence of a power supply source.
Typically, a non-volatile semiconductor memory comprises a matrix of memory cells, e.g., floating gate MOS transistors; each memory cell has a threshold voltage adapted to be programmed to different levels, corresponding to different logic values.
The so-called flash memory is a very popular type of non-volatile memory, which also exhibits the capability of electrically writing and erasing the memory cells.
For example, each memory cell of a two-level flash memory is adapted to store a single information bit. In an erased condition, the generic memory cell has a relatively low threshold voltage (associated by convention with the logic value “1”); the memory cell is programmed by injecting electrons into its floating gate: in this condition the memory cell has a higher threshold voltage (associated by convention with the logic value “0”).
Multilevel flash memories comprise memory cells capable of storing more than just one information bit. Each memory cell can be programmed to one of a plurality of different states, each corresponding to a respective range of threshold voltage values. For example, each memory cell of a four-level flash memory stores a logic value consisting of two information bits (“11”, “10”, “01” e “00”, with the logic value “11” that is associated with the lowest threshold voltage range and the logic value “00” that is associated with the highest threshold voltage range).
In order to retrieve the stored information, semiconductor memories comprise reading circuits, adapted to read the data stored in the memory cells.
Particularly, the data stored in the selected memory cell is read by comparing the behavior of the current flowing through the selected memory cell with the behavior of the current(s) provided by one or more reference cells which are programmed to predetermined states. For this purpose, the reading circuit has to properly bias the selected memory cell and the reference cells.
The comparison between the currents flowing through the selected memory cell and the reference memory cells, respectively, is typically performed by sensing circuits, included in the reading circuit and adapted to generate output signals whose value provide an indication of the logic value stored in the selected memory cell.
A known technique for reading the information stored in the memory cells is the so-called ramp-voltage sensing technique.
Essentially, the ramp-voltage sensing technique comprises two different phases: a precharge phase and an evaluation phase. Before the evaluation phase of the datum stored in the selected memory cell, the precharge phase is required for precharging an access line (e.g., a bit line) coupled to the selected memory cell, to a predetermined potential, in such a way as to charge stray capacitances intrinsically associated therewith. In fact, a current flowing through the bit line causes the charging of the associated stray capacitances, and, accordingly, a corresponding transient is required before the bit line voltage and current reach a steady value. Thus, for avoiding a wrong reading performed during this transient, it is necessary to guarantee that the bit line charging is completed, before performing an evaluation on the logic value stored in the memory cell accessed for reading. Regretfully, the length of this transient depends on a number of factors, such as the operating temperature, the value of a supply voltage of the memory device, and statistical variations of parameters whose values are affected by the manufacturing process.
According to the ramp-voltage sensing technique, the evaluation phase provides for applying a voltage ramp to the control gate of a selected memory cell to be read and to the reference memory cells (having known threshold voltages); the datum stored in the selected memory cell is determined on the basis of a time relationship between the instants at which the selected memory cell and the reference memory cells pass from a first conduction state to a second conduction state. In the practice, the first conduction state corresponds to a sunk current less than a predetermined current and the second conduction state corresponds to a sunk current equal to or exceeding the predetermined current. This sensing technique is particularly suited for the sensing of multi-level memory cells.
A known sensing circuit used for performing both the precharge phase and the evaluation phase according to the ramp-voltage sensing technique is described in European patent application EP1505605.
FIG. 1 shows an exemplary circuit diagram of a known sensing circuit 100 adapted to perform both the precharge and the evaluation according to the ramp-voltage sensing technique. The sensing circuit 100 comprises an amplifier 110, particularly a differential amplifier of relatively high gain, having an inverting input (indicated by the symbol “−”) and a non-inverting input (indicated by the symbol “+”). The inverting input of the amplifier 110 is connected to a circuital node YMS, that is coupled to a selected memory cell MC through a bit line BL. The non-inverting input is instead fed with a reference voltage VREF, having a desired predetermined value which is the target potential of the node YMS. A resistive load element R, typically, a polysilicon resistor, is connected in negative feedback between an output OUTDIF1 of the amplifier 110 and the inverting input thereof. The output OUTDIF1 of the amplifier 110 is also fed to an inverting input of a comparator 120, having a non-inverting input directly connected to the inverting input of the amplifier 110, and thus to the node YMS. An output of the comparator 120 forms an output SA-OUT of the sensing circuit 100. The node YMS is also connected to a reference current generator, providing a reference current IREF to be exploited during the evaluation phase.
FIG. 2 pictorially illustrates the evolution in time of the potentials of the node YMS, the output OUTDIF1 and the output SA-OUT during both the precharge and evaluation phases.
At the beginning of the precharge phase, the capacitance (not shown in the Figure) intrinsically associated with the bit line BL (and thus loading the node YMS) is assumed to be discharged, so the potential of the node YMS is low, approximately equal to a reference (ground) voltage GND. Since the voltage difference between the non-inverting input and the inverting input of the amplifier 110 is positive (it is assumed that the reference voltage VREF is higher than the ground voltage GND), the potential of the output OUTDIF1 assumes a high positive value. Consequently, the amplifier 110 delivers a feedback current IF of relatively high intensity, flowing from the output OUTDIF1 to the node YMS through the resistor R. Also, the reference current IREF flows to the node YMS. In this way, the capacitance of the node YMS is charged, and the potential of the node YMS increases. As long as the potential of the node YMS is lower than the reference voltage VREF, the potential of the output OUTDIF1 is positive. Also, as long as the potential of the output OUTDIF1 is higher than the potential of the node YMS, the feedback current IF flows from the output OUTDIF1 to the node YMS, and the voltage difference between the non-inverting input and the inverting input of the comparator 120 is negative. Consequently, during this period of time, the potential of the output SA-OUT of the comparator 120 is low, for example at a value equal to the ground voltage GND. As the potential of the node YMS increases, the (absolute value of the) potential of the output OUTDIF1 and the (absolute value of the) feedback current IF decrease.
At the end of the precharge phase, the potential of the node YMS reaches the reference voltage VREF, and the feedback current IF starts flowing in the reverse direction, flowing from the node YMS to the output OUTDIF1. In this way, the voltage difference between the node YMS and the output OUTDIF1 is positive and the potential of the output SA-OUT of the comparator 120 switches high, since the potential of its non-inverting terminal becomes higher than the potential of its inverting terminal. Moreover, after a transient, the feedback current IF equals the reference current IREF, and the potential of the node YMS is stable. In this steady-state condition, the voltage difference VR between the node YMS and the output OUTDIF1 is stable, with the node YMS at a potential higher than that of the output OUTDIF1.
Once the precharge phase is terminated, the evaluation phase is started by applying a voltage ramp to the control gate of the selected memory cell MC to be read and to the reference cells. When the voltage ramp reaches a sufficiently high value, the selected memory cell MC begins draining a current IBL from the node YMS, through the bit line BL. The feedback current IF still flows from the node YMS to the output OUTDIF1 but, since the reference current IREF is constant, as the current IBL increases, the (absolute value of the) feedback current IF decreases.
When, due to the increase in the gate voltage, the current IBL reaches and exceeds the reference current IREF, the feedback current IF reverses its direction, flowing from the output OUTDIF1 to the node YMS and this in turn causes the reverse in the sign of the voltage difference VR across the resistor R. In fact, the potential of the output OUTDIF1 exceeds the potential of the node YMS at an inversion time IT, as depicted in FIG. 2. In this way, the potential of the output SA-OUT of the comparator 120 switches again low (e.g., to the ground voltage GND) at a switching instant SW right after the inversion time IT. The delay between the inversion time IT and the switching instant SW depends on the switching speed of the comparator 120.
The switching instant SW of the comparator 120 is then exploited for retrieving the datum stored into the selected memory cell MC: the higher the threshold voltage of the selected memory cell MC, the later the switching instant SW occurs. More in particular, the switching instant SW in respect of the selected cell to be read is compared to a switching instant SWREF for a reference memory cell having a known predetermined threshold voltage, determined using a sensing circuit identical to the circuit 100. If the switching instant SW occurs before the switching instant SWREF, the threshold voltage of the selected memory cell MC is lower than the threshold voltage of the reference memory cell, and vice versa.
The Applicant has observed that the known sensing circuit 100 for the ramp-voltage sensing technique described in the foregoing is affected by some problems.
First of all, the sensing circuit 100 is very sensitive to variations of the reference current IREF and to disturbs affecting the reference voltage VREF, the potential of the node YMS and the potential of the output OUTDIF1. Since the inversion time IT (and the switching instant SW of the comparator 120) strongly depends on the voltage difference VR at the end of the precharge phase, the lower the intensity of the reference current IREF, the higher the sensitivity to the disturbs of the sensing circuit 100, because the voltage difference VR between the node YMS and the output OUTDIF1 is made smaller. Variations of the reference current IREF may delay or anticipate the switching instant SW, and consequently increase the uncertainty of the evaluation of the datum stored in the selected memory cell MC.
In order to make the sensing circuit 100 less susceptible to disturbs, it is preferable operating with relatively high voltage differences VR. This means that, with the same reference current IREF, a resistor R having a higher resistance value is needed.
However, in order to integrate a polysilicon resistor R having a relatively high resistance value, a significant area within the semiconductor chip wherein the sensing circuit 100 is integrated is wasted. Furthermore, the resistance values of polysilicon resistors are affected by mismatches, capable in this case of invalidating the evaluation phase and/or increasing the precharge phase duration.
Moreover, by increasing the resistance value of the resistor R too much, the duration of the precharge phase is unfavorably increased, because the intensity of the feedback current IF flowing from the output OUTDIF1 to the node YMS is reduced, and therefore the capacitance of the node YMS takes more time for being charged.
Also, observing again FIG. 2, it can be appreciated that the voltage difference VR between the node YMS and the output OUTDIF1 becomes smaller and smaller (in absolute value) during the final part of the evaluation phase. Consequently, even if a resistor R having a high resistance value is used (so as to obtain an increased voltage difference VR at the end of the precharge phase), a disturb occurring in the final part of the evaluation phase would significantly shift the inversion time IT.
In view of the state of the art outlined in the foregoing, it is an object of the present invention to provide an improved sensing circuit which were not affected by the problems of the known sensing circuits, in particular by the problems discussed above.